1. Field of the Invention
The present invention relates to a data latch circuit and a semiconductor device using the same; and, more particularly, to a data latch circuit and a semiconductor device using the same which is capable of improving the timing margin to latch output data in a DQ block when data is inputted and outputted to and from the semiconductor device and a write operation margin when input data is written in a memory cell.
2. Description of Related Art
As is well known, DRAM (Dynamic Random Access Memory) is a volatile memory device that stores data in each cell having a structure of one transistor and one capacitor where a data input/output operation as basic function of DRAM cell is done by an on/off of a word line of transistor coupled with its gate within each cell.
A conventional device for the data input/output is shown in FIG. 1. As shown in FIG. 1, in the conventional DRAM memory device, a memory cell region is comprised of a plurality of banks. And, a read operation of the data stored in each cell is made by transmitting the cell date amplified by input/output (IO) sense amplifiers through global input/output (IO) lines and then latching them through transfer gates, gate0, gate1, . . . , by their transfer to DQ blocks. Further, a write operation of data to each cell from the outside is done by transmitting external data to write drivers from the DQ blocks through the global IO lines and then storing them in each memory cell.
Herein, details of a process of transferring cell data to each DQ block and latching it by its own block will be explained in the following. That is, data stored in each cell are amplified by the IO sense amplifiers and then transferred to the transfer gates gate0, gate1, . . . , installed at a preceding part of the DQ blocks through the global IO lines. And, the transfer gates gate0, gate1, . . . , conduct an on/off operation by a certain pin strobe signal pin_strobe for transferring the data to the DC blocks.
In the above, the strobe signal strobe generally refers to a control signal used for transmission of data, which indicates a short pulse signal for synchronization of data transmission during a transmission and reception of data in a computer system. And, the pin strobe signal pin_strobe is of a type of the strobe signal and used for synchronization of data transmission to the DQ blocks through the global IO lines.
In FIG. 1, the transfer gates gate0, gate1, . . . , are enabled or disabled in response to the pin strobe signals pin_strobe, thus transferring the cell data to the DC blocks. In other words, if the pin strobe signal pin_strobe is low level, then the transfer gates gate0, gate1, . . . , are turned-on and thus the cell data is transferred to the DC blocks for its latch. In contrary, if the pin strobe signal pin_strobe is transited to a high level, the transfer gates gate0, gate1, . . . , are turned-off, allowing for no transfer of the cell data to the DQ blocks.
However, in the conventional semiconductor device, there occurs non-synchronization in the data transmission upon a high-speed operation, resulting in the output of incorrect data. That is, in case the semiconductor device is operated at high speed, there exists a phenomenon that arises a level transition of cell data toturn-on the transfer gates gate0, gate1, . . . , due to the enabling of the pin strobe signal pin_strobe that issues since a difference of skew and flight time of data that are transited every one clock period is large. For this reason, data to be transferred to the DQ blocks at the next clock period is transferred and latched thereto in the current period.
FIG. 2 is a waveform showing the problems mentioned above. As shown, in the conventional semiconductor device, there appears a phenomenon that an interval where the pin strobe signal is low level, indicating that the transfer gates gate0, gate1, . . . , are enabled, and an interval where cell data from the global IO lines is transited from a high level (or low level) to a low level (or high level) overlap each other. This shows the fact that incorrect data can be transferred to the DQ blocks.
On the other hand, in the above, although presented is an instance where the cell data is provided to the DQ blocks, such situation may occuran instance that external data is transmitted via the global IO lines and then stored in each memory cell by the write drivers. That is, in this case, there exists a problem in that incorrect data is written in cell data since there is non-synchronization for data transmission between a write strobe signal wt_strobe for operating the write drivers and input data.